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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs
Rev. 02 -- 4 June 2009 Objective data sheet
1. General description
The ADC1410S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1410S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. The device also includes a programmable gain amplifier with a flexible input voltage range. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1410S is ideal for use in communications, imaging and medical applications.
1.5
005aaa040
1.5
005aaa041
0 dB
005aaa042
1
1 -40
0.5
0.5
0
0 -80
-0.5
-0.5
-1
-1 -120
-1.5 0 4000 8000 12000 16000
-1.5 0 4000 8000 12000 16000
0
10
20
30 f (MHz)
40
Fig 1.
Integral Non-Linearity (INL)
Fig 2.
Differential Non-Linearity (DNL)
Fig 3.
Output spectrum: -1 dBFS, 80 Msps, fi = 4.43 MHz
2. Features
I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps 14-bit pipelined ADC core Single 3 V supply Flexible input voltage range: 1 V to 2 V p-p with 6 dB programmable fine gain I CMOS or LVDS DDR digital outputs I INL 1 LSB, DNL 0.5 LSB (typical) I I I I I I Input bandwidth, 600 MHz Power dissipation, 387 at 80 Msps SPI Interface Duty cycle stabilizer Fast OTR detection Offset binary, 2's complement, gray code I Power-down and Sleep modes I HVQFN40 package
NXP Semiconductors
ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
3. Applications
I Wireless and wired broadband communications I Spectral analysis I Portable instrumentation I Ultrasound equipment I Imaging systems
4. Ordering information
Table 1. Ordering information fs (Msps) Package Name ADC1410S125HN/C1 125 ADC1410S105HN/C1 105 ADC1410S080HN/C1 80 ADC1410S065HN/C1 65 Description Version SOT618-1 SOT618-1 SOT618-1 SOT618-1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm Type number
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
5. Block diagram
SCLK/DFS SDIO/ODS
ADC1410S
ERROR CORRECTION AND DIGITAL PROCESSING PGA SPI INTERFACE OTR CMOS: DAV or LVDS/DDR: DAVP DAVM CMOS: D13 to D0 or LVDS/DDR: D13_M to D0_M D13_P to D0_P
INP T/H INPUT STAGE INM ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS
CLOCK INPUT STAGE AND DUTY CYCLE CONTROL
SYSTEM REFERENCE AND POWER MANAGEMENT
CS
PWD OE
VCM
VREF
SENSE
AGND
OGND
CLKM
CLKP
VDDO
REFB
VDDA
REFT
005aaa036
Fig 4. Block diagram
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
6. Pinning information
6.1 Pinning
37 SDIO/ODS 36 SCLK/DFS
39 SENSE
34 OGND
33 VDDO
37 SDIO/ODS
36 SCLK/DFS
39 SENSE
34 OGND
33 VDDO
40 VREF
35 OTR
38 CS
terminal 1 index area REFB REFT AGND VCM VDDA AGND INM INP AGND 1 2 3 4 5 6 7 8 9
31 DAV
32 n.c.
REFB 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 24 D6 23 D7 22 D8 21 D9 REFT AGND VCM VDDA AGND INM INP AGND
1 2 3 4 5 6 7 8 9
38 CS
terminal 1 index area
31 DAVM 30 D0_D1_P 29 D0_D1_M 28 D2_D3_P 27 D2_D3_M 26 D4_D5_P 25 D4_D5_M 24 D6_D7_P 23 D6_D7_M 22 D8_D9_P 21 D8_D9_M D10_D11_P 20
005aaa038
ADC1410S HVQFN40
ADC1410S HVQFN40
VDDA 10 VDDA 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D12_D13_M 17 D12_D13_P 18 D10_D11_M 19
VDDA 10 VDDA 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D13 17 D12 18 D11 19 D10 20
005aaa037
Transparent top view
Transparent top view
Fig 5.
Pin configuration with CMOS digital outputs selected
Fig 6.
Pin configuration with LVDS/DDR digital outputs selected
6.2 Pin description
Table 2. Symbol REFB REFT AGND VCM VDDA AGND INM INP AGND VDDA VDDA CLKP CLKM DEC OE PWD
ADC1410S065_080_105_125_2
Pin description (CMOS digital outputs) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type [2] O O G O P G I I G P P I I O I I Description bottom reference top reference analog ground common-mode output voltage analog power supply analog ground complementary analog input analog input analog ground analog power supply analog power supply clock input complementary clock input regulator decoupling node output enable, active LOW power down, active HIGH
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Objective data sheet
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32 DAVP
40 VREF
35 OTR
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
Pin description (CMOS digital outputs) Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Type [2] O O O O O O O O O O O O O O O P G O I I/O I I I/O Description data output bit 13 (MSB) data output bit 12 data output bit 11 data output bit10 data output bit 9 data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (LSB) data valid output clock not connected output power supply output ground out of range SPI clock / data format select SPI data IO / output data standard SPI chip select reference programming pin voltage reference input/output
Table 2. Symbol D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3. Symbol
Pin description (LVDS/DDR) digital outputs) Pin [1] 17 18 19 20 21 22 23 24 25 26 27 28 29 Type [2] O O O O O O O O O O O O O Description differential output data D12 and D13 multiplexed, complement differential output data D12 and D13 multiplexed, true differential output data D10 and D11 multiplexed, complement differential output data D10 and D11 multiplexed, true differential output data D8 and D9 multiplexed, complement differential output data D8 and D9 multiplexed, true differential output data D6 and D7 multiplexed, complement differential output data D6 and D7 multiplexed, true differential output data D4 and D5 multiplexed, complement differential output data D4 and D5 multiplexed, true differential output data D2 and D3 multiplexed, complement differential output data D2 and D3 multiplexed, true differential output data D0 and D1 multiplexed, complement
D12_D13_M D12_D13_P D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
Pin description ...continued (LVDS/DDR) digital outputs) Pin [1] 30 31 32 Type [2] O O O Description differential output data D0 and D1 multiplexed, true data valid output clock, complement data valid output clock, true
Table 3. Symbol D0_D1_P DAVM DAVP
[1] [2]
Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDO VCC Tstg Tamb Tj Parameter analog supply voltage output supply voltage supply voltage difference storage temperature ambient temperature junction temperature VDDA - VDDO Conditions Min -55 -40 Max +125 +85 Unit V V V C C C
8. Thermal characteristics
Table 5. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ
Unit K/W K/W
In compliance with JEDEC test board, in free air.
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
9. Static characteristics
Table 6. Static characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; min and max values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol Supplies VDDA VDDO IDDA IDDO analog supply voltage output supply voltage analog supply current output supply current CMOS mode LVDS DDR mode fclk = 125 Msps; fi =70 MHz CMOS mode; fclk = 125 Msps; fi =70 MHz LVDS DDR mode: fclk = 125 Msps; fi =70 MHz P power dissipation ADC1410S125 ADC1410S105 ADC1410S080 ADC1410S065 Power-down mode Sleep mode Clock inputs: pins CLKP and CLKM AC coupled; LVPECL, LVDS and sine wave Vi(clk)dif LVCMOS VI VIL VIH IIL IIH VIL VIH IIL IIH CI input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance 0.3VDDA 0 2 -10 0 0.7VDDA -10 -50 4 0.7VDDA V 0.8 VDDA +10 V V A A Logic Inputs: pins PWD and OE differential clock input voltage peak-to-peak 0.2 0.8 V 2.85 1.65 2.85 3.0 1.8 3.0 185 20 35 557 488 387 336 2 40 3.4 3.6 3.6 V V V mA mA mA mW mW mW mW mW mW Parameter Conditions Min Typ Max Unit
Serial Peripheral Interface: pins CS, SDIO/ODS, SCLK/DFS 0.3VDDA V VDDA +10 +50 V A A pF
Digital Outputs: CMOS mode - pins D13 to D0, OTR, DAV Output levels, VDDO = 3 V VOL VOH IOL IOH LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current IOL = IOH = 3-state; output level = 0 V 3-state; output level = VDDA OGND 0.8VDDO 0.2VDDO V VDDO V A A
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
Table 6. Static characteristics ...continued Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; min and max values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Symbol CO VOL VOH Parameter output capacitance LOW-level output voltage HIGH-level output voltage Conditions high impedance; OE = HIGH IOL = IOH = Min OGND 0.8VDDO Typ 3 Max Unit pF
Output levels, VDDO = 1.8 V 0.2VDDO V VDDO V
Digital Outputs, LVDS mode - pins D13P, D13M to D0P, D0M, DAVP and DAVM Output levels, VDDO = 3 V only, Rload = 100 VO(offset) VO(dif) CO II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) VVREF Accuracy INL DNL Eoffset EG Supply PSRR power supply rejection ratio 100 mV (p-p) on VDDA 35 dBc integral non-linearity differential non-linearity offset error gain error guaranteed no missing codes -5 -0.95 1 0.5 2 0.5 +5 +0.95 LSB LSB mV %FS output offset voltage differential output voltage output capacitance Input current Input resistance Input capacitance common mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current voltage on pin VREF output input peak-to-peak VINP = VINM output buffer current set to 3.5 mA output buffer current set to 3.5 mA -5 0.9 1 0.5 VDDA/2 0.5 to 1 1.2 350 5 1.5 600 +5 2 2 1 V mV pF A pF V MHz V V A V V
Analog inputs: pins INP and INM
Common mode output voltage: pin VCM
I/O reference voltage: pin VREF
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7. Dynamic characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; min and max values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V; VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS at LVDS interface; unless otherwise specified. Symbol Parameter Conditions ADC1410S065 Min Analog signal processing 2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-tonoise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SFDR spuriousfree dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz IMD Intermodul- fi = 3 MHz ation fi = 30 MHz distortion fi = 70 MHz fi = 170 MHz 94 93 90 88 92 91 90 88 88 87 86 83 94 93 91 88 93 92 90 87 88 87 86 83 96 92 91 85 91 91 90 88 87 87 85 82 96 93 91 85 90 89 87 87 87 86 84 82 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc ADC1410S080 ADC1410S105 ADC1410S125 Unit Typ Ma x Typ Max Min Typ Max Min Typ Max Min
11.9 11.7 11.6 11.6 73.2 72.4 71.8 71.3 91 90 89 86 94 93 92 89 -
11.9 11.7 11.6 11.5 73.1 72.3 71.8 71.2 91 90 89 86 94 93 92 89 -
11.8 11.7 11.6 11.5 72.9 72.3 71.7 71.1 90 90 88 85 93 93 91 88 -
11.8 11.7 11.6 11.5 72.5 72.2 71.6 71 90 89 87 85 93 92 90 88 -
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
10.2 Clock and digital output timing
Table 8. Clock and digital output timing characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF; min and max values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V ; VINP - VINM = -1 dBFS; unless otherwise specified. Symbol Parameter Conditions ADC1410S065 Min Clock timing input: pins CLKP and CLKM fclk tlat(data) clk clock frequency data latency time clock duty cycle DCS_EN = 1 DCS_EN = 0 td(s) twake sampling delay time wake-up time propagation DATA delay DAV set-up time hold time rise time[1] DATA DAV tf tPD fall time[1] DATA 20 30 45 14 50 50 0.8 tbd 65 70 55 60 30 45 14 50 50 0.8 tbd 80 70 55 60 30 45 14 50 50 0.8 tbd 105 70 55 60 30 45 14 50 50 0.8 tbd 125 70 55 MHz clk/cy % % ns ns Typ Max ADC1410S080 Min Typ Max ADC1410S105 Min Typ Max ADC1410S125 Min Typ Max Unit
CMOS Mode Timing output: pins D13 to D0 and DAV tPD tsu th tr 0.5 0.5 0.5 3.9 4.2 7.7 6.7 3.9 4.2 2.4 2.4 2.4 0.5 0.5 0.5 3.9 4.2 6.5 5.5 3.9 4.2 2.4 2.4 2.4 0.5 0.5 0.5 3.9 4.2 4.7 3.8 3.9 4.2 2.4 2.4 2.4 0.5 0.5 0.5 3.9 4.2 4.3 3.5 3.9 4.2 2.4 2.4 2.4 ns ns ns ns ns ns ns ns ns
LVDS DDR mode timing output: pins D13P, D13M to D0P, D0M, DAVP and DAVM propagation DATA delay DAV
[1]
Measured between 20 % to 80 % of VDDO; rise time measured from -50 mV to +50 mV; fall time measured from +50 mV to -50 mV.
ADC1410S065_080_105_125_2
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
10.3 SPI Timings
Table 9. Characteristics Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 C and CL = 5 pF. Min and max values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDO = 1.8 V Symbol SPI timings tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max) SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time hold time maximum clock frequency data to SCLKH CS to SCLKH data to SCLKH CS to SCLKH 40 16 16 5 5 2 2 25 ns ns ns ns ns ns ns MHz Parameter Conditions Min Typ Max Unit
ADC1410S065_080_105_125_2
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
11. Application information
11.1 Device control
The ADC1410S can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (PIN control mode).
11.1.1 SPI and PIN control modes
The device enters PIN control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI settings are ignored. SPI control mode is enabled by forcing pin CS LOW. It is not possible to toggle between PIN control and SPI control modes. Once SPI control mode has been enabled, the device will remain in this mode until it is powered down. The transition from PIN control mode to SPI control mode is illustrated in Figure 7.
CS
PIN control mode Data Format offset binary
SPI control mode
SCLK/DFS
Data Format 2's complement LVDS DDR
SDIO/ODS
CMOS
R/W
W1
W0
A12
005aaa039
Fig 7. Control mode selection.
When the device enters SPI control mode, the output data standard (CMOS or LVD DDR) is not determined by the state of the relevant SPI control bit (LVDS/CMOS; see Table 21), but by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS (SDIO = LOW = CMOS).
11.1.2 Operating mode selection
The active ADC1410S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 18) or using pins PWD and OE in PIN control mode, as described in Table 10.
Table 10. Pin PWD 0 0 1 1 Operating mode selection via pin PWD and OE Pin OE 0 1 0 1 Operating mode Power-up Power-up Sleep Power-down Output high-Z no yes yes yes
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 21) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected.
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, 2's complement or gray code; see Table 21) or using pin DFS in PIN control mode (offset binary or 2's complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, 2's complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1410S supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 20 further details). The equivalent circuit of the sample and hold input stage, including ESD protection and circuit and package parasitics, is shown in Figure 8.
Package
ESD
Parasitics
Switch INP 8
Ron = 14 4 pF
internal clock
Sampling Capacitor
INM
7
Ron = 14
Switch
4 pF
internal clock
Sampling Capacitor
005aaa043
Fig 8.
Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 9) is needed to counteract the effects of charge injection generated by the sampling capacitance.
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively.
R
INP
C
R
INM
005aaa073
Fig 9.
Anti-kickback circuit
The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth.
Table 11. 3 MHz 70 MHz 170 MHz RC coupling versus input frequency - recommended values R 25 12 12 C 12 pF 8 pF 8 pF
Input frequency
11.2.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 10 would be suitable for a baseband application.
ADT1-1WT
100 nF
Analog lnput
100 nF 25
25
INP
12 pF 100 nF 25 25
100 nF
INM VCM
100 nF
100 nF
005aaa044
Fig 10. Single transformer configuration suitable for baseband applications
The configuration shown in Figure 11 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance.
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
ADT1-1WT
100 nF 50
ADT1-1WT
50
12
INP
Analog lnput
8.2 pF 50 50 12
INM VCM
100 nF
100 nF
100 nF
005aaa045
Fig 11. Dual transformer configuration suitable for high frequency application
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1410S has a stable and accurate built-in internal reference voltage. This reference voltage can be set internally, externally or via the SPI (programmable in 1 dB steps between 0 dB and -6 dB via control bits INTREF when bit INTREF_EN = 1; see Table 20). The equivalent reference circuit is shown in Figure 12.
REFT REFERENCE AMP REFB
VREF
BUFFER
BANDGAP REFERENCE
ADC CORE SENSE SELECTION LOGIC
005aaa046
Fig 12. Single transformer configuration suitable for baseband applications
If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 12.
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Objective data sheet
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NXP Semiconductors
ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
Reference selection SPI bit INTREF_EN 0 0 0 1 SENSE pin AGND VREF pin 330 pF capacitor to AGND full scale (p-p) 2V
Table 12. Selection internal internal external
pin VREF connected to pin SENSE and via 1 V a 330 pF capacitor to AGND VDDA external voltage between 0.5 V and 1 V[1] 1 V to 2 V
internal via SPI
[1]
pin VREF connected to pin SENSE and via 1 V to 2 V 330 pF capacitor to AGND
The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source.
VREF
REFT
330 pF
VREF
REFT
330 pF
SENSE
REFB
SENSE
REFB
005aaa047
005aaa048
Fig 13. Internal reference, 2 V (p-p) full scale
Fig 14. Internal reference, 1 V (p-p) full scale
VREF
REFT
VREF
0.1 F
REFT
330 pF
SPI SETTINGS INTREF_EN = 1, active INTREF = XXX SENSE REFB
V
SENSE
REFB
005aaa049
VDDA
005aaa050
Fig 15. Internal reference via SPI, 1 V to 2 V (p-p) full scale
Fig 16. External reference, 1 V to 2 V (p-p) full scale
11.3.2 Gain control
The gain is programmable between 0 dB to -6 dB in 1 dB steps via the SPI (see Table 20). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of the ADC1410S. The corresponding full scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 13:
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Objective data sheet
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ADC1410S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps
Reference SPI Gain Control Gain 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB reserved full scale (p-p) 2V 1.78 V 1.59 V 1.42 V 1.26 V 1.12 V 1V x
Table 13. INTREF 000 001 010 011 100 101 110 111
11.3.3 Common-mode output voltage (VO(cm))
A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point.
PACKAGE
ESD
PARASITICS COMMON MODE REFERENCE
1.5 V VCM
0.1 F
ADC CORE
005aaa051
Fig 17. Equivalent schematic of the common-mode reference circuit
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V. The graph in Figure 18 illustrates how the SFDR and SNR characteristics vary with changes in the common-mode input voltage.
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dB SFDR (x MHz)
SNR (x MHz)
0.9 V
2V
VI(cm) 005aaa052
Fig 18. SFDR and SNR performances versus VI(cm)
11.4 Clock input
11.4.1 Drive modes
The ADC1410S can be driven differentially (SINE, LVPECL or LVDS) without the performance being affected by the choice of configuration. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor).
LVCMOS Clock lnput
CLKP CLKM LVCMOS Clock lnput
CLKP CLKM
005aaa053
Fig 19. LVCMOS Single-ended clock input
CLKP Sine Clock lnput
Sine Clock lnput
CLKP
CLKM
CLKM
005aaa054
Fig 20. Sine differential clock input
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CLKP LVDS Clock lnput
CLKM
005aaa055
Fig 21. LVDS differential clock input
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 22. The common-mode voltage of the differential input stage is set via internal 5 k resistors.
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk) SE_SEL SE_SEL
5k
5k
CLKM
005aaa056
Fig 22. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface (see Table 19). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 19), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %.
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11.4.4 Clock input divider
The ADC1410S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 19). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 21). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 23. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.4 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF.
VDDO PARASITICS ESD PACKAGE
LOGIC DRIVER
50
Dx
OGND
005aaa057
Fig 23. CMOS digital output buffer
The output resistance is 50 and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 28):
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 21).
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3.5 mA typ - +
VCCO
DnP/Dn + 1P DnM/Dn + 1M 100 RECEIVER
+
- OGND
005aaa058
Fig 24. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 resistor (typical) at the receiver side (Figure 24) or internally via SPI control bits LVDS_INTTER (see Figure 25 and Table 30).
3.5 mA typ - +
VCCO
DxP/Dx + 1P 100 DxM/Dx + 1M RECEIVER
+
- OGND
005aaa059
Fig 25. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI and DATAI; see Table 29) in order to adjust the output logic voltage levels.
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1410S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 26 and Figure 27 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. By default, pin OTR goes HIGH fourteen clock cycles after an OTR event has occurred. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see Table 27). When Fast OTR is enabled, OTR goes HIGH four clock cycles after the OTR event. The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET.
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11.5.5 Digital offset
By default, the ADC1410S delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET; see Table 23).
11.5.6 Test patterns
For test purposes, the ADC1410S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL; see Table 24). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 25 and Table 26) and is selected when TESTPAT_SEL = 101. The selected test pattern will be transmitted regardless of the analog input.
11.5.7 Output codes versus input voltage
Table 14. VINP - VINM < -1 -1 -0.9998779 -0.9997559 -0.9996338 -0.9995117 .... -0.0002441 -0.0001221 0 +0.0001221 +0.0002441 .... +0.9995117 +0.9996338 +0.9997559 +0.9998779 +1 > +1 Output codes Offset binary 00 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 00 0000 0000 0011 00 0000 0000 0100 .... 01 1111 1111 1110 01 1111 1111 1111 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 .... 11 1111 1111 1011 11 1111 1111 1100 11 1111 1111 1101 11 1111 1111 1110 11 1111 1111 1111 11 1111 1111 1111 Two's complement 10 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 10 0000 0000 0011 10 0000 0000 0100 .... 11 1111 1111 1110 11 1111 1111 1111 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 .... 01 1111 1111 1011 01 1111 1111 1100 01 1111 1111 1101 01 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 OTR pin 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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11.6 Timings summary
11.6.1 CMOS mode timings
N N+1
td(s) N+2 tclk CLKP CLKM tPD (N - 14) (N - 13) (N - 12) (N - 11)
DATA tPD
tsu
th
DAV
tclk
005aaa060
Fig 26. CMOS mode timing
11.6.2 LVDS DDR mode timing
N N+1
td(s) N+2 tclk CLKP CLKM tPD Dx_Dx + 1_P Dx Dx_Dx + 1_M tsu th tsu th DAVP DAVM tclk
005aaa061
(N - 14)
(N - 13)
(N - 12)
(N - 11)
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
tPD
Fig 27. LDVS DDR mode timing
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11.7 Serial Peripheral Interface (SPI)
11.7.1 Register description
The ADC1410S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 16).
Table 15. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7
[1] [2]
LSB 6 W1[2] A6 5 W0[2] A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0
Bit R/W indicates whether it is a read (1) or a write (0) operation. Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 16).
Table 16. W1 0 0 1 1
Number of data bytes to be transferred after the instruction bytes W0 0 1 0 1 Number of bytes transmitted 1 byte 2 bytes 3 bytes 4 bytes or more
Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incriminated to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission.
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CS
SCLK SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
Fig 28. SPI mode timing
11.7.2 Default modes at start-up
During circuit initialization, it doesn't matter which output data standard has been selected. At power-up, the device defaults to PIN control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1410S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 29). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 21. When the ADC1410S enters SPI control mode, the output data format (2's complement or offset binary) is determined by the level on pin SCLK (grey code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT in Table 21.
CS
SCLK (Data Format)
SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at startup
005aaa063
Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK (Data Format)
SDIO (CMOS LVDS DDR)
2's complement, CMOS default mode at startup
005aaa064
Fig 30. Default mode at start-up: SCLK HIGH = 2's complement; SDIO LOW = CMOS
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11.7.3 Register allocation map
Table 17. Register allocation map R/W Bit definition Bit 7 R/W SW_ RST R/W R/W R/W R/W R/W R/W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 INTREF DATA_FORMAT Bit 1 OP_MODE CLKDIV Bit 0 Default Bin 0000 0000 DCS_EN 0000 0001 0000 0000 0000 0000 0000 1110 0000 0000 TESTPAT_SEL 0000 0000 0000 0000 DAVI_ x2_EN DAVI FASTOTR DAV_DRV FASTOTR_DET DATA_DRV DATAI_x DATAI 2_EN BIT/BYTE_ LVDS_INTTER WISE 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000 Addr Register name Hex 0005 Reset and operating mode 0006 Clock 0008 Internal reference 0011 Output data standard. 0012 Output clock 0013 Offset 0014 Test pattern 1 0015 Test pattern 2 0016 Test pattern 2 0017 Fast OTR 0020 CMOS output 0021 LVDS DDR O/P 1 0022 LVDS DDR O/P 2
SE_SEL DIFF/SE LVDS/ CMOS INTREF_ EN OUTBUF DAVINV
DAVPHASE
DIG_OFFSET -
R/W TESTPAT_USER R/W TESTPAT_USER R/W R/W R/W R/W -
Table 18. Bit 7
Reset and operating mode control register (address 0005h) bit description Access R/W 0 1 Value Description reset digital section no reset performs a reset of the digital section operating mode 00 01 10 11 normal (Power-up) Power-down Sleep normal (Power-up)
Symbol SW_RST
6 to 2 reserved 1 to 0 OP_MODE R/W
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Clock control register (address 0006h)bit description Access Value R/W 0 1 Description single-ended clock input pin select CLKM CLKP differential/single ended clock input select 0 1 fully differential single-ended clock input divide by 2 0 1 disabled enabled duty cycle stabilizer 0 1 disabled enabled
Table 19. Bit 4
Symbol SE_SEL
7 to 5 reserved
3
DIFF/SE
R/W
2 1
reserved CLKDIV R/W
0
DCS_EN
R/W
Table 20. Bit 3
Internal reference control register (address 0008h) bit description Access R/W 0 1 Value Description programmable internal reference enable disable active programmable internal reference 000 001 010 011 100 101 110 111 0 dB (FS = 2 V) -1 dB (FS = 1.78 V) -2 dB (FS = 1.59 V) -3 dB (FS = 1.42 V) -4 dB (FS = 1.26 V) -5 dB (FS = 1.12 V) -6 dB (FS = 1 V) reserved
Symbol INTREF_EN
7 to 4 reserved
2 to 0 INTREF
R/W
Table 21. Bit 4
Output data standard control register (address 0011h) bit description Access R/W 0 1 Value Description output data standard: LVDS DDR or CMOS CMOS LVDS DDR output buffers enable 0 1 output enabled output disabled (high Z)
Symbol LVDS/CMOS
7 to 5 reserved
3
OUTBUF
R/W
2
ADC1410S065_080_105_125_2
reserved
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Output data standard control register (address 0011h) bit description ...continued Access R/W 00 01 10 11 Value Description output data format offset binary 2's complement gray code offset binary
Table 21. Bit
Symbol
1 to 0 DATA_FORMAT
Table 22. Bit 3
Output clock register (address 0012h) bit description Access R/W 0 1 Value Description output clock data valid (DAV) polarity normal inverted DAV phase select 000 001 010 011 100 101 110 111 output clock shifted (ahead) by 3 ns output clock shifted (ahead) by 2.5 ns output clock shifted (ahead) by 2 ns output clock shifted (ahead) by 1.5 ns output clock shifted (ahead) by 1 ns output clock shifted (ahead) by 0.5 ns default value as defined in timing section output clock shifted (delayed) by 0.5 ns
Symbol DAVINV
7 to 4 reserved
2 to 0 DAVPHASE
R/W
Table 23. Bit
Offset register (address 0013h) bit description Access R/W 011111 ... 000000 ... 100000 ... 0 ... -32 LSB Value Description digital offset adjustment +31 LSB
Symbol
7 to 6 reset 5 to 0 DIG_OFFSET
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Test pattern register 1(address 0014h) bit description Access Value R/W 000 001 010 011 100 101 110 111 Description digital test pattern select off mid scale -FS +FS toggle `1111..1111'/'0000..0000' custom test pattern `1010..1010.' `010..1010'
Table 24. Bit
Symbol
7 to 3 reserved 2 to 0 TESTPAT_SEL
Table 25. Bit
Test pattern register 2 (address 0015h) bit description Access Value R/W Description custom digital test pattern (bits 13 to 6)
Symbol
7 to 0 TESTPAT_USER Table 26. Bit
Test pattern register 3 (address 0016h) bit description Access Value R/W Description custom digital test pattern (bits 5 to 0)
Symbol
7 to 2 TESTPAT_USER 1 to 0 reserved Table 27. Bit 3
Fast OTR register (address 0017h) bit description Access Value R/W 0 1 Description fast Out-of-Range (OTR) detection disabled enabled set fast OTR detect level 000 001 010 011 100 101 110 111 -20.56 dB -16.12 dB -11.02 dB -7.82 dB -5.49 dB -3.66 dB -2.14 dB -0.86 dB
Symbol FASTOTR
7 to 4 reset
2 to 0 FASTOTR_DET
R/W
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CMOS output register (address 0020h) bit description Access R/W 00 01 10 11 Value Description drive strength for DAV CMOS output buffer low medium high very high drive strength for DATA CMOS output buffer 00 01 10 11 low medium high very high
Table 28. Bit
Symbol
7 to 4 reserved 3 to 2 DAV_DRV
1 to 0 DATA_DRV
R/W
Table 29. Bit 7 to 6 5
LVDS DDR output register 1 (address 0021h) bit description Access R/W 0 1 Value Description double LVDS current for DAV LVDS buffer disabled enabled LVDS current for DAV LVDS buffer 00 01 10 11 3.5 mA 4.5 mA 1.25 mA 2.5 mA double LVDS current for DATA LVDS buffer 0 1 disabled enabled LVDS current for DATA LVDS buffer 00 01 10 11 3.5 mA 4.5 mA 1.25 mA 2.5 mA
Symbol DAVI_x2_EN
4 to 3 DAVI
R/W
2
DATAI_x2_EN
R/W
1 to 0 DATAI
R/W
Table 30. Bit 3
LVDS DDR output register 2 (address 0022h) bit description Access Value Description DDR mode for LVDS output 0 1 bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge)
Symbol
7 to 4 reserved BIT/BYTE_WISE R/W
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LVDS DDR output register 2 (address 0022h) bit description ...continued Access Value Description R/W 000 001 010 011 100 101 110 111 internal termination for LVDS buffer (DAV and DATA) no internal termination 300 180 110 150 100 81 60
Table 30. Bit
Symbol
2 to 0 LVDS_INTTER
11.7.4 Serial timing interface
SPI timing is shown in Figure 31.
tsu CS
th
tsu
tw(SCLKL) tw(SCLK) tw(SCLKH)
th
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 31. SPI timing
SPI timing characteristics are detailed in Table 9.
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12. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm
SOT618-1
D
B
A
terminal 1 index area E A A1
c
detail X
e1 e 11 L 10 21 e
1/2 e
C b 20 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area
30 40 Dh 0 2.5 scale E(1) 6.1 5.9 Eh 4.25 3.95 e 0.5 e1 4.5 e2 4.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 31 X
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 6.1 5.9 Dh 4.25 3.95
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT618-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 32. Package outline SOT618-1 (HVQFN40)
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13. Revision history
Table 31. Revision history Release date 20090604 Data sheet status Objective data sheet Objective data sheet Change notice Supersedes ADC1410S065_080_105_125_1 Document ID ADC1410S065_080_105_125_2 Modifications: ADC1410S065_080_105_125_1
*
Values in Table 7 have been updated
20090528
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14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Single 14-bit ADC 65, 80, 105 or 125 Msps
16. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Clock and digital output timing . . . . . . . . . . . . 10 SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 12 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI and PIN control modes . . . . . . . . . . . . . . 12 Operating mode selection. . . . . . . . . . . . . . . . 12 Selecting the output data standard . . . . . . . . . 12 Selecting the output data format. . . . . . . . . . . 13 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13 Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System reference and power management . . 15 Internal/external references . . . . . . . . . . . . . . 15 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Common-mode output voltage (VO(cm)) . . . . . 17 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Equivalent input circuit . . . . . . . . . . . . . . . . . . 19 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 19 Clock input divider . . . . . . . . . . . . . . . . . . . . . 20 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital output buffers: CMOS mode . . . . . . . . 20 Digital output buffers: LVDS DDR mode . . . . . 20 Data valid (DAV) output clock . . . . . . . . . . . . . 21 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 21 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output codes versus input voltage . . . . . . . . . 22 Timings summary . . . . . . . . . . . . . . . . . . . . . . 23 CMOS mode timings. . . . . . . . . . . . . . . . . . . . 23 LVDS DDR mode timing . . . . . . . . . . . . . . . . . 23 11.7 11.7.1 11.7.2 11.7.3 11.7.4 12 13 14 14.1 14.2 14.3 14.4 15 16 Serial Peripheral Interface (SPI). . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Serial timing interface. . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 25 26 31 32 33 34 34 34 34 34 34 35
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 June 2009 Document identifier: ADC1410S065_080_105_125_2

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